1. Field of the Invention
The present invention relates generally to microprocessors, and more particularly to methods for testing microprocessors.
2. Description of Related Art
A large majority of digital products, such as computers, utilize one or more microprocessors that implement and manage the functions of the product. Currently, many companies that provide digital equipment to the consumer marketplace, often outsource the fabrication of the microprocessors to one or more suppliers specializing in production of the microprocessors.
It is important to catch defects in the microprocessor device early in the fabrication stage while costs associated with the defect are lower than in later stages. Once the microprocessor is further assembled at later stages into larger components, such as circuit boards, failure of the microprocessor can result in substantial cost escalation, such as costs to rework a circuit board. If the microprocessor fails when assembled in the final product, the costs can be even greater and the marketplace reputation of the company can be affected.
To ensure end reliability of the final product, the outsourcing company typically requires the supplier to test each microprocessor utilizing specialized test equipment to ensure the microprocessor meets a required standard of quality assurance and reliability. As a microprocessor can contain hundreds of thousands of gates and functionalities, the outsourcing company's engineering group typically generates a large amount of test patterns, also termed test vectors, to ensure the test equipment adequately tests each gate and functionality requirement of the microprocessor. Thus, the resulting test vector set can be very large.
In many instances, the memory space required to run the complete test vector set is larger in size than the test equipment memory capacity. When this occurs, the test package is truncated into multiple, smaller segments, termed test vector sub-sets, which are incrementally loaded into the test equipment memory to accommodate the limited test equipment memory size. Multiple insertions, or loads, of the test vector sub-sets significantly add to microprocessor production costs paid by the outsourcing supplier, and are an inefficient use of the microprocessor supplier's production cycles.
FIG. 1 illustrates a block diagram of a microprocessor test process having multiple pre-burn-in and post-burn-in test vector sub-set insertions found in the prior art. In the present example, the microprocessor test process 100 includes three phases: a pre-burn-in test phase 102, a burn-in phase 104, and a post-burn-in test phase 106. Due to the limited memory capacity of the test equipment used in test process 100, the complete test vector set is truncated into three segments, test vector sub-set 1 (TVSS 1), test vector sub-set 2 (TVSS 2), and test vector sub-set 3 (TVSS 3).
After microprocessor fabrication, such as on a wafer, wafer sort and assembly, a supplier initiates pre-burn-in testing of the microprocessors. In pre-burn-in test phase 102, at process 108, the supplier loads test vector sub-set 1 into the memory of the test equipment. At process 110, the test equipment executes test vector sub-set 1 in testing the microprocessors. When test vector sub-set 1 testing is complete, at process 112, test vector sub-set 2 is loaded into memory, and, at process 114, the test equipment executes test vector sub-set 2. When test vector sub-set 2 testing is complete, at process 116, test vector sub-set 3 is loaded into memory and, at process 118, the test equipment executes test vector sub-set 3. Thus, three insertions, or loads, into test equipment memory, were needed to run the complete test vector set during pre-burn-in test phase 102. When pre-burn-in test phase 102 is complete, burn-in phase 104 begins, during which, at process 120, the microprocessors are burned in. Burn-in is a process where the field life expectancy is re-created in a shorter amount of time by operating the microprocessor at higher voltage and temperature to accelerate the early life fails termed infant mortality.
Following burn-in phase 104, post-burn-in test phase 106 begins, during which the supplier essentially repeats the tests used in pre-burn-in test phase 102. At process 122, test vector sub-set 1 is loaded into the memory of the test equipment, and, at process 124, the test equipment executes test vector sub-set 1. At process 126, test vector sub-set 2 is loaded into memory, and, at process 128, test vector sub-set 2 is executed. At process 130, test vector sub-set 3 is loaded into memory, and, at process 132, test vector sub-set 3 is executed. After test process 100 is complete, the approved microprocessors can be further processed, such as by the addition of latch attachments and packaging for shipment.
As described above, test process 100 requires six test vector sub-set insertions, e.g., processes 108, 112, 116, 122, 126 and 130, in order for a complete test vector set to be executed in the pre-burn-in test phase 102 and in the post-burn-in test phase 106. Due to the typically large size of each test vector sub-set, the load time of each test vector sub-set into the test equipment memory can take hours, and this load time is in addition to the time spent actually testing the microprocessors, e.g., executing each test vector sub-set. This procedure can be expensive as the supplier typically charges the outsourcing company for time spent loading each test vector sub-set plus a per test insertion charge. Further, the testing equipment throughput of the supplier goes down, as the supplier's production shift spends significant time waiting for the test equipment memory to be loaded rather than actively testing microprocessors. Thus output efficiency of the test equipment is reduced and the price per unit produced increases substantially.